ESD Mitigation in Electronic Product Design

I came across a very good article about ESD mitigation recently in EDN Magazine [1].  The design approach occurs in three tiers.  First keep the ESD out by keeping everything enclosed in a metal chassis connected to earth ground.  Almost all useful products have holes in the chassis though for interaction with the outside world.  So there are bound to be some ESD paths.  The second tier of defense is to dissipate the ESD energy either with series impedance elements (ferrite beads or resistors) or dump the energy out to chassis ground immediately.  The third tier is the protection at the silicon and board level of sensitive inputs.  Clamping diodes are used in the silicon and series impedance elements and or shunt capacitors can be used at the board level to prevent ESD events from upsetting normal operation.

I recently debugged an ESD problem on a product with an exposed metal piece that was not directly tied to chassis ground.  So the ESD path to earth ground was not controlled.  Its a sure bet that the energy was finding some path, probably capacitively coupling to chassis ground.  After spending a lot of time trying to improve the path to earth ground, it was eventually discovered that a single board computer in the design tied its mounting holes to digital logic ground.  Those mounting holes were connected to the chassis.  So that was a path where ESD energy could couple into and affect the digital logic.  Logic ground and chassis ground were only supposed to be tied together at a single point near the power supply in this design.

[1] Henehan, Burke. February 1, 2007. “Maximizing EOS and ESD Immunity in High-Performance Serial Buses.” EDN Magazine pp 77-82.